1. Field of the Invention
The invention relates to memory and input/output space data control systems used in computer systems, and more particularly to systems utilizing direct memory access techniques.
2. Description of the Related Art
Personal computer systems are becoming increasingly prevalent and increasingly more powerful. Computer systems have always had the problem of transferring information from a device to memory for use by the computer and from memory to various devices for storage or operation purposes. In early personal computer designs these transfers between the memory space and the input/output space associated with various peripheral devices such as disk controllers, displays, keyboards, and serial or parallel interface units were directly performed by the microprocessor in the computer system. As the capabilities of the various devices increased this transfer task became a burden on the microprocessor and other approaches were developed to free the microprocessor from this effort. One of these approaches was direct memory access (DMA), where a different controller handled the task of coordinating and performing the transfers once the necessary transfer information was provided to the DMA controller. The DMA controller was provided with the memory address information and other parameters. When operating, the DMA controller provided the address values to the system bus and drive the various control signals as necessary to cause the transfer operation to occur between the memory space and the I/O space.
This DMA technique was incorporated into the original IBM PC produced by International Business Machines Corp. (IBM). The IBM PC was based on the Intel Corporation (Intel) 8088 microprocessor, which had 20 address lines and transferred data over an 8 bit wide path. The DMA controller included in the IBM PC therefore only needed to use a 20 bit address and transfer data in one byte packages. This original DMA controller had eight channels, allowing transfers between eight different devices and memory to be programmed and operate without further microprocessor attention.
The capabilities of the devices and components that could be used and incorporated in personal computers continued to advance and users requested the advances to allow more complex programs to be developed and used. Eventually the IBM PC, and its hard disk-based relative, the PC/XT, were considered unsatisfactory. IBM introduced the IBM PC/AT or AT, utilizing the Intel 80286 microprocessor and incorporating more advanced capabilities. The 80286 and the AT could use 24 bits of address information and could transfer data over a 16 bit bus. However, this extended addressing capability and need to handle two data widths necessitated redesign of the DMA system. The DMA system was redesigned to handle the wider address and data buses, with certain channels designated for byte operations and certain channels designated for word operation.
Once again, the capabilities of components and peripheral devices proceeded to increase and users continued to demand the performance available. Several different events occurred in an attempt to help resolve the performance demand situation. One event was the introduction by IBM of the PS/2 line of personal computers. One perceived limitation of the AT was the inefficient method of allowing for multiple bus masters. A bus master is a device which can take full control of the system buses for its own purposes. The general cases where bus masters are used are cases which need greater peripheral performance than available using a DMA controller. Members of the PS/2 line utilized the MicroChannel Architecture or MCA to improve bus mastering capabilities, as well as other system capabilities. The operation of the MCA is more fully defined in the IBM Personal System/2 Model 80 Technical Reference Manual, bearing a copyright date of 1987 and published by IBM.
The MCA utilized a revised DMA control system. The DMA control system was compatible with previous computer programs but offered extended features not previously available, including a different method of providing the DMA controller with the information necessary for its operation. The extended method of providing the information utilized passing memory address information uniformly through two input/output (I/O) space locations or I/O ports, instead of the 16 I/O ports previously needed. A channel was selected at a first I/O port and the address information was passed through a second I/O port. The DMA controller also operated in two phases, a first phase where the data to be transferred was read and a second phase where the data was written, instead of the single phase operation used in the previous systems.
However, the DMA system in the MCA was limited in that it could only utilize 24 bits of address. The host microprocessor and the bus masters could utilize 32 bits of address information, but the DMA controller was limited to 24 bits. These 24 bits were provided conventionally or through three successive accesses to the new I/O port.
An additional limitation of the DMA controller was that data could not be readily transferred between an I/O port and a memory location starting on an odd address using word wide operations. The data could only effectively be interchanged with the memory in byte wide operations. For example, during a DMA read operation, the DMA controller obtained the data from the memory in bytes, assembled the individual bytes into the proper word and then transferred this word to the I/O port of the device. This resulted in DMA operations that took much longer than necessary to operate and thus reduced the performance of the computer system.
An additional problem with computer systems implementing the MCA was that if a device having only a 24 bit wide address, such as the DMA controller or a bus master, were driving the system bus, the upper 8 bits of the address bus were floated. This presented a cache coherency problem should a cache controller be present in the computer system. A cache controller is used in conjunction with cache memory to increase the performance of the computer system. Cache memory is fast memory which allows the microprocessor to operate at full speed, unlike main memory which, for cost reasons, is slower and often reduces the speed of the microprocessor from maximum available rates. Identical copies of data are contained in both memories, with the cache controller noting when main memory locations are accessed and deleting that reference in the cache. The cache controller uses all 32 bits of address to perform its tasks, but when the upper 8 bits of the address bus are floating there is no guarantee that the cache controller is receiving the same address as the involved memory units. Thus a possible coherency problem between the data maintained in the cache memory and in the main memory may result during 24 bit address MCA operations.
The second event of interest was the introduction of the 80386 microprocessor by Intel. This was an enhanced machine that had a full 32 bit address and could operate using 32 bit wide data. The use of this microprocessor allowed the capabilities of the computer system to be greatly enhanced. Users could access vast amounts of memory if desired and transfer data at very high rates over a 32 bit data bus. The large address space allowed programmers to use as much space as needed to position applications where desired, not where forced.
However, a problem occurred when the 80386 was used in an MCA machine. The 80386 used 32 address lines, but the DMA system in the MCA used only 24 address lines. Thus the freedom made available to programmers by the use of the 80386 was taken away if DMA operations were to be performed because of the 24 bit address limitation.